A desynchronizer is commonly used in the telephony industry to convert a data stream of varying instantaneous frequency into a data stream of fixed frequency. Typically, a first-in first-out memory (FIFO) is used as an intermediate data buffer and a phase-locked loop feedback technique is used to control the desynchronizer output frequency. Analog phase detector techniques have been used in conjunction with analog filters and analog oscillators to implement the phase-locked loop circuitry. Because of component count and cost considerations in addition to tolerance errors of an analog design, it is desirable to implement the phase-locked loop circuitry digitally.
Conventional digital implementations have generally required very high clock frequencies in order to obtain the phase resolution needed for the phase-locked loop feedback computations. For example, to obtain a phase resolution of one-sixteenth unit interval of a 1.544 MHz clock, a high speed sample clock of 24.704 MHz is required. The high clock frequency requirements are disadvantageous due to the amount of power typically required to generate them, high levels of interference noises associated therewith, and generally require more expensive circuit components.
Accordingly, it has become desirable to provide apparatus and a method for monitoring the depth of a desynchronizer FIFO with fractional-bit resolution without requiring excessively high internal clock frequencies.